Janhvi Gohel

Dedicated professional with over 6 years of experience in Physical Design and Static Timing Analysis aimed at converging low power design, resolving issues, and improving performance. Capabilities in delivering partitions from RTL to GDS, Timing Closure, and Final sign-off on advanced technology nodes with expertise in automating tasks for team building in quick convergence.

Working as Partition Owner for High-performance Intel Architecture Cores and responsible for

▪ Complete execution of partitions from RTL to GDS, Timing Closure, and Final sign-off on advanced technology node (10nm and below)

▪ Performing a wide range of back-end activities, including logic synthesis, DFT, macros-based floor planning,placement, CTS (Clock Tree Synthesis, route, PnR (Place and Route), STA (Static Timing Analysis), clocking, power grid analysis, thermal, physical verification, DRC, Power Optimization, and design closure.

▪ Converge partition with 4.5million gate count from syn to lv handoff

• Key member of P-core design team working on Intel’s latest CPUs in the latest process technology.

• Proposed and implemented different methods to reduce net delay and transition to overcome backend-related timing challenges. Published a paper based on this as a first author in Intel DTTC-2023.

• Handled a whole section of 9 partitions in which I converged all partitions, ran FCT, analyzed timing, completed all quality checks, and delivered to LV prior to the deadline.

• Worked as Section Timing Owner [4 different projects], and Section Caliber Owner [3 different projects] including projects such as Graphics, Core, IPU, and SOC level

▪ Timing execution and convergence including setup and hold for greater than 5Ghz Freq and low-power digital designs of the significant partition of Intel core

▪ Multi Corner Static Timing Analysis

▪ Closely working with Layout and Floor planning team

▪ RTL feedback for area reduction and timing convergence

• Expertise in physical design and STA by using EDA tools such as Fusion Compiler, ICCompiler2, Genus, Innovus, StarRC, Primetime, Caliber

• Proficient in hierarchical design approach, top-down design, area budgeting, timing budgeting, and physical verification convergence

• Successfully developed automation to achieve quick power and timing convergence

• Developed script to place repeaters at some particular distance in design based on their I/O position

• Effectively communicated complex engineering design processes to teams at the project and organization level

• Guided internship graduates to make them understand medium complex functional unit blocks to ensure successful delivery in a timely manner 

M.Tech in Electronics and Communication B.E in Electronics and Communication

Nirma University, Ahmedabad, India Gujarat Technological University, Bhavnagar, India

2016-2018