Naga Sai Theja Malipeddi

Highly motivated Master's degree student with hands-on experience as a part time employee in the SOC Physical Implementation team. Skilled in floorplanning, place & route, power analysis and power optimizations.

Topic: Power optimal physical implementation of a LDPC error correction unit of flash memory controller in 22nm FDSOI technology utilizing adaptive body bias.

Description: Researched on various error correction circuitry implementations specifically for flash memory devices. Explored various techniques in 22nm FDSOI technology to optimize circuits for power, performance, and area. Implementing the LDPC error correction circuit including all steps needed till final tape out ready database like floorplanning, placement, clock tree synthesis and routing. Physical and Timing signoff. Static and Dynamic power analysis.

Highly motivated Master's degree student with hands-on experience as a part time employee in the SOC Physical Implementation team. Skilled in floorplanning, place & route, power analysis and power optimizations.