Sayanti Pal

As part of my work as a product engineer, I work on library development of standard cells using Liberate Trio. I perform characterization and generate power and delay models (NLDM, CCS, CCSN, CCSP, ECSM) for standard cells at different technology nodes. I also worked on Verilog library development and back-annotation using tempus.

Cadence Design Systems, Bangalore May, 2022– Present
Product Engineer I
● Characterization of standard cells using Liberate. Liberate tool uses spice netlists, model files and template files as input and generates Library for standard cells in .lib format. Template files contain user data i.e., process, temperature range, operating voltage, slew rate. All the input files are written TCL.
● Statistical characterization is run using Variety. Variety tools uses the same inputs as Liberate and along with those inputs, variation parameters (i.e., standard deviation, mean etc.) are given as input.
● Timing validation for different delay models are performed using Liberate. Generally, NLDM, CCS, ECSM and CCSN models are used to validate the timing.
● Verilog library generation using Liberate Trio and aging analysis flow testing.
NXP Semiconductors, Bangalore July, 2021– April 2022
V&V and Test Engineer
● Light sensor sensitivity checks on silicon using SMU control. White light sensitivity was checked on bare silicon using different light intensities by providing current from Source Meter Unit (SMU). Keithely 2601B automated was used for setting source current and instrument was automated using TSP commands in python. Behavior of the chip was verified with different light intensities.
● Custom testbench preparation for checking application layer commands in python. ISO 15693 standard commands and tag specific commands were verified for real life use-case from a customer point of view.
● Software requirements verified for NFC reader (Open Controller) firmware using LPC and pn5190 board. Mainly I am verifying Crypto blocks using AES-128/256, RSA, ECC with SHA 256/384/512.
Prudent Engineering Co. 24Parganas, WB July, 2017 – December, 2018
● Supervision of erection and commissioning of 6.3 MVA 33/11 KV Transformer Bay, 50 MVA 132/33 KV Transformer Bay, 33KV and 132 KV line bay etc. at different Sub-Stations under WBSETCL.

Defense Institute of Advanced Technology (DIAT-DRDO) 2019-2021
M.Tech in VLSI and Embedded Systems CGPA 8.32/10
National Institute of Technology (NIT), Durgapur 2013-2017
B.Tech in Electrical Engineering CGPA 8.23 /10