Digital Design - München, Deutschland - Synopsys

Beschreibung

Job Description and RequirementsThe ASIC design engineer is responsible primarily for generating and verifying high quality RTL design for the Synopsys High Speed Ethernet DesignWare IP.

The work on the ASIC design engineer includes block and function definition, detailed specification, RTL coding and Code verification.

The design engineer collaborates with the Design and Verification Team to write test plans, troubleshoot the RTL code and supports the Lint, CDC, Synthesis and physical design activities with the objective to meet the quality, performance required for ASIC IPs.

The required skills and knowledge are:

• Excellent knowledge in RTL Verilog and System Verilog Language, coding and code simulation technics
• Experience in Ethernet system design
• Knowledge of UVM required to support the Design Verification Team would be a plusOur Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world's broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. Self-driving cars. The Internet of Things. And we're powering it all with the world's most advanced technologies for chip design and software security.

Job CategoryEngineering CountryGermany Job SubcategoryASIC Digital Design Hire TypeEmployeeRequisition Number: 36890BRHiring Location:
GERMANY - Munich