Master Thesis Student - Walldorf, Deutschland - SAP

SAP

Geprüftes Unternehmen

Walldorf, Deutschland

vor 2 Wochen

Geschrieben von:

Lena Wagner

beBee Recruiter

Beschreibung

What we offer

ABOUT THE TEAM

The HANA Database Campus team organizes the work with students and the research activities within the HANA & Analytics teams.

THE ROLE

Context of the project

Field-programmable gate arrays (FPGAs) have been shown to excel at speeding-up graph algorithms (Yao, However, even highly optimized graph processing accelerators still suffer from a memory bottleneck (Dann, Thus, FPGA resources remain underutilized and allow implementing additional processing steps without negatively impacting performance of existing parts of the design.

Goal of the project

The goal of this thesis is to combine graph compression techniques (Brisaboa, 2009; Claude, 2010) with a FPGA-based graph processing accelerator to virtually increase the memory bandwidth.

This means utilizing an in-line decompression step paired with a highly effective graph compression technique to alleviate the memory bottleneck.

Tasks for the student

Implement graph decompression subsystem on FPGA
Combine with our graph processing accelerator
Analyze performance and resource usage

Related Work
Brisaboa, Nieves R., Susana Ladra, and Gonzalo Navarro. "k2-trees for Compact Web Graph Representation." International symposium on string processing and information retrieval. 2009.
Claude, Francisco, and Gonzalo Navarro. "Fast and compact web graph representations." ACM Transactions on the Web (TWEB
Dann, Jonas, Daniel Ritter, and Holger Fröning. "Demystifying Memory Access Patterns of FPGA-Based Graph Processing Accelerators." Proceedings of the 4th ACM SIGMOD Joint International Workshop on Graph Data Management Experiences & Systems (GRADES) and Network Data Analytics (NDA
Yao, Pengcheng, Long Zheng, Xiaofei Liao, Hai Jin, and Bingsheng He.

"An Efficient Graph Accelerator with Parallel Data Conflict Management." Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques.

2018.

ROLE REQUIREMENTS

Student (f/m/d) at a university or a university of applied sciences
Preferred fields of study: Computer science or electrical engineering
Prior experience in graph processing
Prior experience in FPGA programming (beneficial)
Strong system level programming skills (e.g., C / C++) #Workingstudent #Werkstudent #Internship #Praktikum #Thesis #Germany #Deutschland #Student #HANADatabaseStudent_

We are SAP

Our inclusion promise

SAP's culture of inclusion, focus on health and well-being, and flexible working models help ensure that everyone - regardless of background - feels included and can run at their best.

At SAP, we believe we are made stronger by the unique capabilities and qualities that each person brings to our company, and we invest in our employees to inspire confidence and help everyone realize their full potential.

We ultimately believe in unleashing all talent and creating a better and more equitable world.

EOE AA M/F/Vet/Disability:

Qualified applicants will receive consideration for employment without regard to their age, race, religion, national origin, ethnicity, age, gender (including pregnancy, childbirth, et al), sexual orientation, gender identity or expression, protected veteran status, or disability.